#ifndef MAC_REG_RX_RSFEC_H
#define MAC_REG_RX_RSFEC_H

/* Base address of Module's Register */
#define CSR_RX_RSFEC_BASE (0x8000)

#define CSR_RX_RSFEC_INT_STATUS (CSR_RX_RSFEC_BASE + 0x0)
#define CSR_RX_RSFEC_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x4)
#define CSR_RX_RSFEC_INT_SET (CSR_RX_RSFEC_BASE + 0x8)
#define CSR_RX_RSFEC_LINK_UP_INT_STATUS (CSR_RX_RSFEC_BASE + 0xc)
#define CSR_RX_RSFEC_LINK_UP_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x10)
#define CSR_RX_RSFEC_LINK_UP_INT_SET (CSR_RX_RSFEC_BASE + 0x14)
#define CSR_RX_RSFEC_LINK_DOWN_INT_STATUS (CSR_RX_RSFEC_BASE + 0x18)
#define CSR_RX_RSFEC_LINK_DOWN_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x1c)
#define CSR_RX_RSFEC_LINK_DOWN_INT_SET (CSR_RX_RSFEC_BASE + 0x20)
#define CSR_RX_RSFEC_TIME_OUT_INT_STATUS (CSR_RX_RSFEC_BASE + 0x24)
#define CSR_RX_RSFEC_TIME_OUT_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x28)
#define CSR_RX_RSFEC_TIME_OUT_INT_SET (CSR_RX_RSFEC_BASE + 0x2c)
#define CSR_RX_RSFEC_OVF_INT_STATUS (CSR_RX_RSFEC_BASE + 0x30)
#define CSR_RX_RSFEC_OVF_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x34)
#define CSR_RX_RSFEC_OVF_INT_SET (CSR_RX_RSFEC_BASE + 0x38)
#define CSR_RX_RSFEC_LOC_SER_INT_STATUS (CSR_RX_RSFEC_BASE + 0x3c)
#define CSR_RX_RSFEC_LOC_SER_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x40)
#define CSR_RX_RSFEC_LOC_SER_INT_SET (CSR_RX_RSFEC_BASE + 0x44)
#define CSR_RX_RSFEC_RM_SER_INT_STATUS (CSR_RX_RSFEC_BASE + 0x48)
#define CSR_RX_RSFEC_RM_SER_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x4c)
#define CSR_RX_RSFEC_RM_SER_INT_SET (CSR_RX_RSFEC_BASE + 0x50)
#define CSR_RX_RSFEC_HI_BER_INT_STATUS (CSR_RX_RSFEC_BASE + 0x54)
#define CSR_RX_RSFEC_HI_BER_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x58)
#define CSR_RX_RSFEC_HI_BER_INT_SET (CSR_RX_RSFEC_BASE + 0x5c)
#define CSR_RX_RSFEC_SD_INT_STATUS (CSR_RX_RSFEC_BASE + 0x60)
#define CSR_RX_RSFEC_SD_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x64)
#define CSR_RX_RSFEC_SD_INT_SET (CSR_RX_RSFEC_BASE + 0x68)
#define CSR_RX_RSFEC_SF_INT_STATUS (CSR_RX_RSFEC_BASE + 0x6c)
#define CSR_RX_RSFEC_SF_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x70)
#define CSR_RX_RSFEC_SF_INT_SET (CSR_RX_RSFEC_BASE + 0x74)
#define CSR_RX_RSFEC_PHY_CERR_INT_STATUS (CSR_RX_RSFEC_BASE + 0x78)
#define CSR_RX_RSFEC_PHY_CERR_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x7c)
#define CSR_RX_RSFEC_PHY_CERR_INT_SET (CSR_RX_RSFEC_BASE + 0x80)
#define CSR_RX_RSFEC_PHY_UERR_INT_STATUS (CSR_RX_RSFEC_BASE + 0x84)
#define CSR_RX_RSFEC_PHY_UERR_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x88)
#define CSR_RX_RSFEC_PHY_UERR_INT_SET (CSR_RX_RSFEC_BASE + 0x8c)
#define CSR_RX_RSFEC_IERR_U_INFO (CSR_RX_RSFEC_BASE + 0x90)
#define CSR_RX_RSFEC_IERR_C_INFO (CSR_RX_RSFEC_BASE + 0x94)
#define CSR_RX_RSFEC_IERR_U_CNT (CSR_RX_RSFEC_BASE + 0x98)
#define CSR_RX_RSFEC_IERR_C_CNT (CSR_RX_RSFEC_BASE + 0x9c)
#define CSR_RX_RSFEC_PHY_RSTN (CSR_RX_RSFEC_BASE + 0xa0)
#define CSR_RX_RSFEC_PHY0_SUBPHY_RSTN (CSR_RX_RSFEC_BASE + 0xc0)
#define CSR_RX_RSFEC_PHY2_SUBPHY_RSTN (CSR_RX_RSFEC_BASE + 0xd0)
#define CSR_RX_RSFEC_MEM_INIT_START (CSR_RX_RSFEC_BASE + 0xd8)
#define CSR_RX_RSFEC_MEM_INIT_STATUS (CSR_RX_RSFEC_BASE + 0xdc)
#define CSR_RX_RSFEC_DBG_IERR_INSERT (CSR_RX_RSFEC_BASE + 0xe0)
#define CSR_RX_RSFEC_PHY_DEC_MEM_ADDR_CFG (CSR_RX_RSFEC_BASE + 0x100)
#define CSR_RX_RSFEC_PHY_SU_MEM_ADDR_CFG (CSR_RX_RSFEC_BASE + 0x120)
#define CSR_RX_RSFEC_IDC_PIPE_CFG (CSR_RX_RSFEC_BASE + 0x140)
#define CSR_RX_RSFEC_DEC_ERR_PAT_CFG (CSR_RX_RSFEC_BASE + 0x144)
#define CSR_RX_RSFEC_DEC_ERR_PAT_CFG2 (CSR_RX_RSFEC_BASE + 0x148)
#define CSR_RX_RSFEC_DEC_ERR_PAT_LANE (CSR_RX_RSFEC_BASE + 0x160)
#define CSR_RX_RSFEC_PRBS_MOD_CFG (CSR_RX_RSFEC_BASE + 0x180)
#define CSR_RX_RSFEC_DEC_DFX_CFG (CSR_RX_RSFEC_BASE + 0x184)
#define CSR_RX_RSFEC_DEC_DFX_GAP_CFG (CSR_RX_RSFEC_BASE + 0x188)
#define CSR_RX_RSFEC_DEC_DFX_STATUS (CSR_RX_RSFEC_BASE + 0x190)
#define CSR_RX_RSFEC_PRBS_ERR_CNT (CSR_RX_RSFEC_BASE + 0x194)
#define CSR_RX_RSFEC_PRBS_BIT_CNT (CSR_RX_RSFEC_BASE + 0x198)
#define CSR_RX_RSFEC_PRBS_SYM_CNT (CSR_RX_RSFEC_BASE + 0x19c)
#define CSR_RX_RSFEC_PRBS_CW_CNT (CSR_RX_RSFEC_BASE + 0x1a0)
#define CSR_RX_RSFEC_PRBS_STATUS (CSR_RX_RSFEC_BASE + 0x1a4)
#define CSR_RX_RSFEC_CW_DEC_ALL_CNT (CSR_RX_RSFEC_BASE + 0x1a8)
#define CSR_RX_RSFEC_CW_1SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x1b0)
#define CSR_RX_RSFEC_CW_2SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x1b8)
#define CSR_RX_RSFEC_CW_3SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x1c0)
#define CSR_RX_RSFEC_CW_4SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x1c8)
#define CSR_RX_RSFEC_CW_5SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x1d0)
#define CSR_RX_RSFEC_CW_6SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x1d8)
#define CSR_RX_RSFEC_CW_7SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x1e0)
#define CSR_RX_RSFEC_CW_8SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x1e8)
#define CSR_RX_RSFEC_CW_9SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x1f0)
#define CSR_RX_RSFEC_CW_10SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x1f8)
#define CSR_RX_RSFEC_CW_11SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x200)
#define CSR_RX_RSFEC_CW_12SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x208)
#define CSR_RX_RSFEC_CW_13SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x210)
#define CSR_RX_RSFEC_CW_14SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x218)
#define CSR_RX_RSFEC_CW_15SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x220)
#define CSR_RX_RSFEC_CW_FAIL_ERR_CNT (CSR_RX_RSFEC_BASE + 0x228)
#define CSR_RX_RSFEC_CW_1SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x230)
#define CSR_RX_RSFEC_CW_2SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x238)
#define CSR_RX_RSFEC_CW_3SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x240)
#define CSR_RX_RSFEC_CW_4SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x248)
#define CSR_RX_RSFEC_CW_5SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x250)
#define CSR_RX_RSFEC_CW_6SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x258)
#define CSR_RX_RSFEC_CW_7SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x260)
#define CSR_RX_RSFEC_CW_8SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x268)
#define CSR_RX_RSFEC_CW_9SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x270)
#define CSR_RX_RSFEC_CW_10SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x278)
#define CSR_RX_RSFEC_CW_11SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x280)
#define CSR_RX_RSFEC_CW_12SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x288)
#define CSR_RX_RSFEC_CW_13SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x290)
#define CSR_RX_RSFEC_CW_14SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x298)
#define CSR_RX_RSFEC_CW_15SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x2a0)
#define CSR_RX_RSFEC_SPARE (CSR_RX_RSFEC_BASE + 0x400)
#define CSR_RX_RSFEC_SPARE_CNT (CSR_RX_RSFEC_BASE + 0x404)
#define CSR_RX_RSFEC_PHY0_CONTROL (CSR_RX_RSFEC_BASE + 0x800)
#define CSR_RX_RSFEC_PHY0_HISER_CFG (CSR_RX_RSFEC_BASE + 0x804)
#define CSR_RX_RSFEC_PHY0_HISER_GAP_CFG (CSR_RX_RSFEC_BASE + 0x808)
#define CSR_RX_RSFEC_PHY0_ERR_STA_CFG (CSR_RX_RSFEC_BASE + 0x80c)
#define CSR_RX_RSFEC_PHY0_LINK_TIMEOUT_CFG (CSR_RX_RSFEC_BASE + 0x810)
#define CSR_RX_RSFEC_PHY0_HEE_CFG (CSR_RX_RSFEC_BASE + 0x814)
#define CSR_RX_RSFEC_PHY0_DIAG_CFG (CSR_RX_RSFEC_BASE + 0x818)
#define CSR_RX_RSFEC_PHY0_DEGRADE_SER_CFG (CSR_RX_RSFEC_BASE + 0x81c)
#define CSR_RX_RSFEC_PHY0_DEGRADE_SER_SET (CSR_RX_RSFEC_BASE + 0x820)
#define CSR_RX_RSFEC_PHY0_DEGRADE_SER_CLR (CSR_RX_RSFEC_BASE + 0x824)
#define CSR_RX_RSFEC_PHY0_DEGRADE_SER_CW (CSR_RX_RSFEC_BASE + 0x828)
#define CSR_RX_RSFEC_PHY0_PHY_BER_CFG (CSR_RX_RSFEC_BASE + 0x82c)
#define CSR_RX_RSFEC_PHY0_PHY_BER_SET (CSR_RX_RSFEC_BASE + 0x830)
#define CSR_RX_RSFEC_PHY0_PHY_BER_CLR (CSR_RX_RSFEC_BASE + 0x834)
#define CSR_RX_RSFEC_PHY0_PHY_BER_CW (CSR_RX_RSFEC_BASE + 0x838)
#define CSR_RX_RSFEC_PHY0_HI_BER_SET (CSR_RX_RSFEC_BASE + 0x83c)
#define CSR_RX_RSFEC_PHY0_HI_BER_CLR (CSR_RX_RSFEC_BASE + 0x840)
#define CSR_RX_RSFEC_PHY0_HI_BER_GAP (CSR_RX_RSFEC_BASE + 0x844)
#define CSR_RX_RSFEC_PHY0_SD_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x850)
#define CSR_RX_RSFEC_PHY0_SD_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x854)
#define CSR_RX_RSFEC_PHY0_SF_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x858)
#define CSR_RX_RSFEC_PHY0_SF_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x85c)
#define CSR_RX_RSFEC_PHY0_SD_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0x860)
#define CSR_RX_RSFEC_PHY0_SD_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0x864)
#define CSR_RX_RSFEC_PHY0_SF_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0x868)
#define CSR_RX_RSFEC_PHY0_SF_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0x86c)
#define CSR_RX_RSFEC_PHY0_SD_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x870)
#define CSR_RX_RSFEC_PHY0_SD_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x874)
#define CSR_RX_RSFEC_PHY0_SF_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x878)
#define CSR_RX_RSFEC_PHY0_SF_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x87c)
#define CSR_RX_RSFEC_PHY0_SD_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x880)
#define CSR_RX_RSFEC_PHY0_SD_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x884)
#define CSR_RX_RSFEC_PHY0_SF_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x888)
#define CSR_RX_RSFEC_PHY0_SF_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x88c)
#define CSR_RX_RSFEC_PHY0_STATUS (CSR_RX_RSFEC_BASE + 0x890)
#define CSR_RX_RSFEC_PHY0_RX_HIS_STATUS (CSR_RX_RSFEC_BASE + 0x894)
#define CSR_RX_RSFEC_PHY0_BOND_STATUS (CSR_RX_RSFEC_BASE + 0x898)
#define CSR_RX_RSFEC_PHY0_ISO_STATUS (CSR_RX_RSFEC_BASE + 0x89c)
#define CSR_RX_RSFEC_PHY0_TIME_OUT_STATUS (CSR_RX_RSFEC_BASE + 0x8a0)
#define CSR_RX_RSFEC_PHY0_IDLE_CHK_ERR_CNT (CSR_RX_RSFEC_BASE + 0x8a4)
#define CSR_RX_RSFEC_PHY0_RX_INV_BLOCK_CNT (CSR_RX_RSFEC_BASE + 0x8a8)
#define CSR_RX_RSFEC_PHY0_ERR_BIT_CNT (CSR_RX_RSFEC_BASE + 0x8ac)
#define CSR_RX_RSFEC_PHY0_ERR_SYM_CNT (CSR_RX_RSFEC_BASE + 0x8b0)
#define CSR_RX_RSFEC_PHY0_DEC_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x900)
#define CSR_RX_RSFEC_PHY0_ERR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x908)
#define CSR_RX_RSFEC_PHY0_CORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x910)
#define CSR_RX_RSFEC_PHY0_UNCORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x918)
#define CSR_RX_RSFEC_PHY0_CORR_LANE_SYM_CNT_ (CSR_RX_RSFEC_BASE + 0x940)
#define CSR_RX_RSFEC_PHY0_LANE_COR0_CNT_ (CSR_RX_RSFEC_BASE + 0x980)
#define CSR_RX_RSFEC_PHY0_LANE_COR1_CNT_ (CSR_RX_RSFEC_BASE + 0x9c0)
#define CSR_RX_RSFEC_PHY1_CONTROL (CSR_RX_RSFEC_BASE + 0xa00)
#define CSR_RX_RSFEC_PHY1_HISER_CFG (CSR_RX_RSFEC_BASE + 0xa04)
#define CSR_RX_RSFEC_PHY1_HISER_GAP_CFG (CSR_RX_RSFEC_BASE + 0xa08)
#define CSR_RX_RSFEC_PHY1_ERR_STA_CFG (CSR_RX_RSFEC_BASE + 0xa0c)
#define CSR_RX_RSFEC_PHY1_LINK_TIMEOUT_CFG (CSR_RX_RSFEC_BASE + 0xa10)
#define CSR_RX_RSFEC_PHY1_HEE_CFG (CSR_RX_RSFEC_BASE + 0xa14)
#define CSR_RX_RSFEC_PHY1_DIAG_CFG (CSR_RX_RSFEC_BASE + 0xa18)
#define CSR_RX_RSFEC_PHY1_DEGRADE_SER_CFG (CSR_RX_RSFEC_BASE + 0xa1c)
#define CSR_RX_RSFEC_PHY1_DEGRADE_SER_SET (CSR_RX_RSFEC_BASE + 0xa20)
#define CSR_RX_RSFEC_PHY1_DEGRADE_SER_CLR (CSR_RX_RSFEC_BASE + 0xa24)
#define CSR_RX_RSFEC_PHY1_DEGRADE_SER_CW (CSR_RX_RSFEC_BASE + 0xa28)
#define CSR_RX_RSFEC_PHY1_PHY_BER_CFG (CSR_RX_RSFEC_BASE + 0xa2c)
#define CSR_RX_RSFEC_PHY1_PHY_BER_SET (CSR_RX_RSFEC_BASE + 0xa30)
#define CSR_RX_RSFEC_PHY1_PHY_BER_CLR (CSR_RX_RSFEC_BASE + 0xa34)
#define CSR_RX_RSFEC_PHY1_PHY_BER_CW (CSR_RX_RSFEC_BASE + 0xa38)
#define CSR_RX_RSFEC_PHY1_HI_BER_SET (CSR_RX_RSFEC_BASE + 0xa3c)
#define CSR_RX_RSFEC_PHY1_HI_BER_CLR (CSR_RX_RSFEC_BASE + 0xa40)
#define CSR_RX_RSFEC_PHY1_HI_BER_GAP (CSR_RX_RSFEC_BASE + 0xa44)
#define CSR_RX_RSFEC_PHY1_SD_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xa50)
#define CSR_RX_RSFEC_PHY1_SD_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xa54)
#define CSR_RX_RSFEC_PHY1_SF_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xa58)
#define CSR_RX_RSFEC_PHY1_SF_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xa5c)
#define CSR_RX_RSFEC_PHY1_SD_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0xa60)
#define CSR_RX_RSFEC_PHY1_SD_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0xa64)
#define CSR_RX_RSFEC_PHY1_SF_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0xa68)
#define CSR_RX_RSFEC_PHY1_SF_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0xa6c)
#define CSR_RX_RSFEC_PHY1_SD_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xa70)
#define CSR_RX_RSFEC_PHY1_SD_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xa74)
#define CSR_RX_RSFEC_PHY1_SF_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xa78)
#define CSR_RX_RSFEC_PHY1_SF_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xa7c)
#define CSR_RX_RSFEC_PHY1_SD_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xa80)
#define CSR_RX_RSFEC_PHY1_SD_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xa84)
#define CSR_RX_RSFEC_PHY1_SF_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xa88)
#define CSR_RX_RSFEC_PHY1_SF_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xa8c)
#define CSR_RX_RSFEC_PHY1_STATUS (CSR_RX_RSFEC_BASE + 0xa90)
#define CSR_RX_RSFEC_PHY1_RX_HIS_STATUS (CSR_RX_RSFEC_BASE + 0xa94)
#define CSR_RX_RSFEC_PHY1_BOND_STATUS (CSR_RX_RSFEC_BASE + 0xa98)
#define CSR_RX_RSFEC_PHY1_ISO_STATUS (CSR_RX_RSFEC_BASE + 0xa9c)
#define CSR_RX_RSFEC_PHY1_TIME_OUT_STATUS (CSR_RX_RSFEC_BASE + 0xaa0)
#define CSR_RX_RSFEC_PHY1_IDLE_CHK_ERR_CNT (CSR_RX_RSFEC_BASE + 0xaa4)
#define CSR_RX_RSFEC_PHY1_RX_INV_BLOCK_CNT (CSR_RX_RSFEC_BASE + 0xaa8)
#define CSR_RX_RSFEC_PHY1_ERR_BIT_CNT (CSR_RX_RSFEC_BASE + 0xaac)
#define CSR_RX_RSFEC_PHY1_ERR_SYM_CNT (CSR_RX_RSFEC_BASE + 0xab0)
#define CSR_RX_RSFEC_PHY1_DEC_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xb00)
#define CSR_RX_RSFEC_PHY1_ERR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xb08)
#define CSR_RX_RSFEC_PHY1_CORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xb10)
#define CSR_RX_RSFEC_PHY1_UNCORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xb18)
#define CSR_RX_RSFEC_PHY1_CORR_LANE_SYM_CNT_ (CSR_RX_RSFEC_BASE + 0xb20)
#define CSR_RX_RSFEC_PHY1_LANE_COR0_CNT_ (CSR_RX_RSFEC_BASE + 0xb30)
#define CSR_RX_RSFEC_PHY1_LANE_COR1_CNT_ (CSR_RX_RSFEC_BASE + 0xb40)
#define CSR_RX_RSFEC_PHY2_CONTROL (CSR_RX_RSFEC_BASE + 0xc00)
#define CSR_RX_RSFEC_PHY2_HISER_CFG (CSR_RX_RSFEC_BASE + 0xc04)
#define CSR_RX_RSFEC_PHY2_HISER_GAP_CFG (CSR_RX_RSFEC_BASE + 0xc08)
#define CSR_RX_RSFEC_PHY2_ERR_STA_CFG (CSR_RX_RSFEC_BASE + 0xc0c)
#define CSR_RX_RSFEC_PHY2_LINK_TIMEOUT_CFG (CSR_RX_RSFEC_BASE + 0xc10)
#define CSR_RX_RSFEC_PHY2_HEE_CFG (CSR_RX_RSFEC_BASE + 0xc14)
#define CSR_RX_RSFEC_PHY2_DIAG_CFG (CSR_RX_RSFEC_BASE + 0xc18)
#define CSR_RX_RSFEC_PHY2_DEGRADE_SER_CFG (CSR_RX_RSFEC_BASE + 0xc1c)
#define CSR_RX_RSFEC_PHY2_DEGRADE_SER_SET (CSR_RX_RSFEC_BASE + 0xc20)
#define CSR_RX_RSFEC_PHY2_DEGRADE_SER_CLR (CSR_RX_RSFEC_BASE + 0xc24)
#define CSR_RX_RSFEC_PHY2_DEGRADE_SER_CW (CSR_RX_RSFEC_BASE + 0xc28)
#define CSR_RX_RSFEC_PHY2_PHY_BER_CFG (CSR_RX_RSFEC_BASE + 0xc2c)
#define CSR_RX_RSFEC_PHY2_PHY_BER_SET (CSR_RX_RSFEC_BASE + 0xc30)
#define CSR_RX_RSFEC_PHY2_PHY_BER_CLR (CSR_RX_RSFEC_BASE + 0xc34)
#define CSR_RX_RSFEC_PHY2_PHY_BER_CW (CSR_RX_RSFEC_BASE + 0xc38)
#define CSR_RX_RSFEC_PHY2_HI_BER_SET (CSR_RX_RSFEC_BASE + 0xc3c)
#define CSR_RX_RSFEC_PHY2_HI_BER_CLR (CSR_RX_RSFEC_BASE + 0xc40)
#define CSR_RX_RSFEC_PHY2_HI_BER_GAP (CSR_RX_RSFEC_BASE + 0xc44)
#define CSR_RX_RSFEC_PHY2_SD_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xc50)
#define CSR_RX_RSFEC_PHY2_SD_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xc54)
#define CSR_RX_RSFEC_PHY2_SF_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xc58)
#define CSR_RX_RSFEC_PHY2_SF_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xc5c)
#define CSR_RX_RSFEC_PHY2_SD_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0xc60)
#define CSR_RX_RSFEC_PHY2_SD_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0xc64)
#define CSR_RX_RSFEC_PHY2_SF_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0xc68)
#define CSR_RX_RSFEC_PHY2_SF_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0xc6c)
#define CSR_RX_RSFEC_PHY2_SD_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xc70)
#define CSR_RX_RSFEC_PHY2_SD_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xc74)
#define CSR_RX_RSFEC_PHY2_SF_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xc78)
#define CSR_RX_RSFEC_PHY2_SF_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xc7c)
#define CSR_RX_RSFEC_PHY2_SD_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xc80)
#define CSR_RX_RSFEC_PHY2_SD_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xc84)
#define CSR_RX_RSFEC_PHY2_SF_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xc88)
#define CSR_RX_RSFEC_PHY2_SF_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xc8c)
#define CSR_RX_RSFEC_PHY2_STATUS (CSR_RX_RSFEC_BASE + 0xc90)
#define CSR_RX_RSFEC_PHY2_RX_HIS_STATUS (CSR_RX_RSFEC_BASE + 0xc94)
#define CSR_RX_RSFEC_PHY2_BOND_STATUS (CSR_RX_RSFEC_BASE + 0xc98)
#define CSR_RX_RSFEC_PHY2_ISO_STATUS (CSR_RX_RSFEC_BASE + 0xc9c)
#define CSR_RX_RSFEC_PHY2_TIME_OUT_STATUS (CSR_RX_RSFEC_BASE + 0xca0)
#define CSR_RX_RSFEC_PHY2_IDLE_CHK_ERR_CNT (CSR_RX_RSFEC_BASE + 0xca4)
#define CSR_RX_RSFEC_PHY2_RX_INV_BLOCK_CNT (CSR_RX_RSFEC_BASE + 0xca8)
#define CSR_RX_RSFEC_PHY2_ERR_BIT_CNT (CSR_RX_RSFEC_BASE + 0xcac)
#define CSR_RX_RSFEC_PHY2_ERR_SYM_CNT (CSR_RX_RSFEC_BASE + 0xcb0)
#define CSR_RX_RSFEC_PHY2_DEC_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xd00)
#define CSR_RX_RSFEC_PHY2_ERR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xd08)
#define CSR_RX_RSFEC_PHY2_CORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xd10)
#define CSR_RX_RSFEC_PHY2_UNCORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xd18)
#define CSR_RX_RSFEC_PHY2_CORR_LANE_SYM_CNT_ (CSR_RX_RSFEC_BASE + 0xd20)
#define CSR_RX_RSFEC_PHY2_LANE_COR0_CNT_ (CSR_RX_RSFEC_BASE + 0xd40)
#define CSR_RX_RSFEC_PHY2_LANE_COR1_CNT_ (CSR_RX_RSFEC_BASE + 0xd60)
#define CSR_RX_RSFEC_PHY3_CONTROL (CSR_RX_RSFEC_BASE + 0xe00)
#define CSR_RX_RSFEC_PHY3_HISER_CFG (CSR_RX_RSFEC_BASE + 0xe04)
#define CSR_RX_RSFEC_PHY3_HISER_GAP_CFG (CSR_RX_RSFEC_BASE + 0xe08)
#define CSR_RX_RSFEC_PHY3_ERR_STA_CFG (CSR_RX_RSFEC_BASE + 0xe0c)
#define CSR_RX_RSFEC_PHY3_LINK_TIMEOUT_CFG (CSR_RX_RSFEC_BASE + 0xe10)
#define CSR_RX_RSFEC_PHY3_HEE_CFG (CSR_RX_RSFEC_BASE + 0xe14)
#define CSR_RX_RSFEC_PHY3_DIAG_CFG (CSR_RX_RSFEC_BASE + 0xe18)
#define CSR_RX_RSFEC_PHY3_DEGRADE_SER_CFG (CSR_RX_RSFEC_BASE + 0xe1c)
#define CSR_RX_RSFEC_PHY3_DEGRADE_SER_SET (CSR_RX_RSFEC_BASE + 0xe20)
#define CSR_RX_RSFEC_PHY3_DEGRADE_SER_CLR (CSR_RX_RSFEC_BASE + 0xe24)
#define CSR_RX_RSFEC_PHY3_DEGRADE_SER_CW (CSR_RX_RSFEC_BASE + 0xe28)
#define CSR_RX_RSFEC_PHY3_PHY_BER_CFG (CSR_RX_RSFEC_BASE + 0xe2c)
#define CSR_RX_RSFEC_PHY3_PHY_BER_SET (CSR_RX_RSFEC_BASE + 0xe30)
#define CSR_RX_RSFEC_PHY3_PHY_BER_CLR (CSR_RX_RSFEC_BASE + 0xe34)
#define CSR_RX_RSFEC_PHY3_PHY_BER_CW (CSR_RX_RSFEC_BASE + 0xe38)
#define CSR_RX_RSFEC_PHY3_HI_BER_SET (CSR_RX_RSFEC_BASE + 0xe3c)
#define CSR_RX_RSFEC_PHY3_HI_BER_CLR (CSR_RX_RSFEC_BASE + 0xe40)
#define CSR_RX_RSFEC_PHY3_HI_BER_GAP (CSR_RX_RSFEC_BASE + 0xe44)
#define CSR_RX_RSFEC_PHY3_SD_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xe50)
#define CSR_RX_RSFEC_PHY3_SD_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xe54)
#define CSR_RX_RSFEC_PHY3_SF_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xe58)
#define CSR_RX_RSFEC_PHY3_SF_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xe5c)
#define CSR_RX_RSFEC_PHY3_SD_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0xe60)
#define CSR_RX_RSFEC_PHY3_SD_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0xe64)
#define CSR_RX_RSFEC_PHY3_SF_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0xe68)
#define CSR_RX_RSFEC_PHY3_SF_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0xe6c)
#define CSR_RX_RSFEC_PHY3_SD_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xe70)
#define CSR_RX_RSFEC_PHY3_SD_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xe74)
#define CSR_RX_RSFEC_PHY3_SF_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xe78)
#define CSR_RX_RSFEC_PHY3_SF_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xe7c)
#define CSR_RX_RSFEC_PHY3_SD_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xe80)
#define CSR_RX_RSFEC_PHY3_SD_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xe84)
#define CSR_RX_RSFEC_PHY3_SF_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xe88)
#define CSR_RX_RSFEC_PHY3_SF_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xe8c)
#define CSR_RX_RSFEC_PHY3_STATUS (CSR_RX_RSFEC_BASE + 0xe90)
#define CSR_RX_RSFEC_PHY3_RX_HIS_STATUS (CSR_RX_RSFEC_BASE + 0xe94)
#define CSR_RX_RSFEC_PHY3_BOND_STATUS (CSR_RX_RSFEC_BASE + 0xe98)
#define CSR_RX_RSFEC_PHY3_ISO_STATUS (CSR_RX_RSFEC_BASE + 0xe9c)
#define CSR_RX_RSFEC_PHY3_TIME_OUT_STATUS (CSR_RX_RSFEC_BASE + 0xea0)
#define CSR_RX_RSFEC_PHY3_IDLE_CHK_ERR_CNT (CSR_RX_RSFEC_BASE + 0xea4)
#define CSR_RX_RSFEC_PHY3_RX_INV_BLOCK_CNT (CSR_RX_RSFEC_BASE + 0xea8)
#define CSR_RX_RSFEC_PHY3_ERR_BIT_CNT (CSR_RX_RSFEC_BASE + 0xeac)
#define CSR_RX_RSFEC_PHY3_ERR_SYM_CNT (CSR_RX_RSFEC_BASE + 0xeb0)
#define CSR_RX_RSFEC_PHY3_DEC_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xf00)
#define CSR_RX_RSFEC_PHY3_ERR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xf08)
#define CSR_RX_RSFEC_PHY3_CORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xf10)
#define CSR_RX_RSFEC_PHY3_UNCORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xf18)
#define CSR_RX_RSFEC_PHY3_CORR_LANE_SYM_CNT_ (CSR_RX_RSFEC_BASE + 0xf20)
#define CSR_RX_RSFEC_PHY3_LANE_COR0_CNT_ (CSR_RX_RSFEC_BASE + 0xf30)
#define CSR_RX_RSFEC_PHY3_LANE_COR1_CNT_ (CSR_RX_RSFEC_BASE + 0xf40)
#define CSR_RX_RSFEC_PHY4_CONTROL (CSR_RX_RSFEC_BASE + 0x1000)
#define CSR_RX_RSFEC_PHY4_HISER_CFG (CSR_RX_RSFEC_BASE + 0x1004)
#define CSR_RX_RSFEC_PHY4_HISER_GAP_CFG (CSR_RX_RSFEC_BASE + 0x1008)
#define CSR_RX_RSFEC_PHY4_ERR_STA_CFG (CSR_RX_RSFEC_BASE + 0x100c)
#define CSR_RX_RSFEC_PHY4_LINK_TIMEOUT_CFG (CSR_RX_RSFEC_BASE + 0x1010)
#define CSR_RX_RSFEC_PHY4_HEE_CFG (CSR_RX_RSFEC_BASE + 0x1014)
#define CSR_RX_RSFEC_PHY4_DIAG_CFG (CSR_RX_RSFEC_BASE + 0x1018)
#define CSR_RX_RSFEC_PHY4_DEGRADE_SER_CFG (CSR_RX_RSFEC_BASE + 0x101c)
#define CSR_RX_RSFEC_PHY4_DEGRADE_SER_SET (CSR_RX_RSFEC_BASE + 0x1020)
#define CSR_RX_RSFEC_PHY4_DEGRADE_SER_CLR (CSR_RX_RSFEC_BASE + 0x1024)
#define CSR_RX_RSFEC_PHY4_DEGRADE_SER_CW (CSR_RX_RSFEC_BASE + 0x1028)
#define CSR_RX_RSFEC_PHY4_PHY_BER_CFG (CSR_RX_RSFEC_BASE + 0x102c)
#define CSR_RX_RSFEC_PHY4_PHY_BER_SET (CSR_RX_RSFEC_BASE + 0x1030)
#define CSR_RX_RSFEC_PHY4_PHY_BER_CLR (CSR_RX_RSFEC_BASE + 0x1034)
#define CSR_RX_RSFEC_PHY4_PHY_BER_CW (CSR_RX_RSFEC_BASE + 0x1038)
#define CSR_RX_RSFEC_PHY4_HI_BER_SET (CSR_RX_RSFEC_BASE + 0x103c)
#define CSR_RX_RSFEC_PHY4_HI_BER_CLR (CSR_RX_RSFEC_BASE + 0x1040)
#define CSR_RX_RSFEC_PHY4_HI_BER_GAP (CSR_RX_RSFEC_BASE + 0x1044)
#define CSR_RX_RSFEC_PHY4_SD_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1050)
#define CSR_RX_RSFEC_PHY4_SD_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1054)
#define CSR_RX_RSFEC_PHY4_SF_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1058)
#define CSR_RX_RSFEC_PHY4_SF_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x105c)
#define CSR_RX_RSFEC_PHY4_SD_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1060)
#define CSR_RX_RSFEC_PHY4_SD_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1064)
#define CSR_RX_RSFEC_PHY4_SF_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1068)
#define CSR_RX_RSFEC_PHY4_SF_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0x106c)
#define CSR_RX_RSFEC_PHY4_SD_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1070)
#define CSR_RX_RSFEC_PHY4_SD_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1074)
#define CSR_RX_RSFEC_PHY4_SF_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1078)
#define CSR_RX_RSFEC_PHY4_SF_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x107c)
#define CSR_RX_RSFEC_PHY4_SD_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1080)
#define CSR_RX_RSFEC_PHY4_SD_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1084)
#define CSR_RX_RSFEC_PHY4_SF_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1088)
#define CSR_RX_RSFEC_PHY4_SF_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x108c)
#define CSR_RX_RSFEC_PHY4_STATUS (CSR_RX_RSFEC_BASE + 0x1090)
#define CSR_RX_RSFEC_PHY4_RX_HIS_STATUS (CSR_RX_RSFEC_BASE + 0x1094)
#define CSR_RX_RSFEC_PHY4_BOND_STATUS (CSR_RX_RSFEC_BASE + 0x1098)
#define CSR_RX_RSFEC_PHY4_ISO_STATUS (CSR_RX_RSFEC_BASE + 0x109c)
#define CSR_RX_RSFEC_PHY4_TIME_OUT_STATUS (CSR_RX_RSFEC_BASE + 0x10a0)
#define CSR_RX_RSFEC_PHY4_IDLE_CHK_ERR_CNT (CSR_RX_RSFEC_BASE + 0x10a4)
#define CSR_RX_RSFEC_PHY4_RX_INV_BLOCK_CNT (CSR_RX_RSFEC_BASE + 0x10a8)
#define CSR_RX_RSFEC_PHY4_ERR_BIT_CNT (CSR_RX_RSFEC_BASE + 0x10ac)
#define CSR_RX_RSFEC_PHY4_ERR_SYM_CNT (CSR_RX_RSFEC_BASE + 0x10b0)
#define CSR_RX_RSFEC_PHY4_DEC_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1100)
#define CSR_RX_RSFEC_PHY4_ERR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1108)
#define CSR_RX_RSFEC_PHY4_CORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1110)
#define CSR_RX_RSFEC_PHY4_UNCORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1118)
#define CSR_RX_RSFEC_PHY4_CORR_LANE_SYM_CNT_ (CSR_RX_RSFEC_BASE + 0x1120)
#define CSR_RX_RSFEC_PHY4_LANE_COR0_CNT_ (CSR_RX_RSFEC_BASE + 0x1140)
#define CSR_RX_RSFEC_PHY4_LANE_COR1_CNT_ (CSR_RX_RSFEC_BASE + 0x1160)
#define CSR_RX_RSFEC_PHY5_CONTROL (CSR_RX_RSFEC_BASE + 0x1200)
#define CSR_RX_RSFEC_PHY5_HISER_CFG (CSR_RX_RSFEC_BASE + 0x1204)
#define CSR_RX_RSFEC_PHY5_HISER_GAP_CFG (CSR_RX_RSFEC_BASE + 0x1208)
#define CSR_RX_RSFEC_PHY5_ERR_STA_CFG (CSR_RX_RSFEC_BASE + 0x120c)
#define CSR_RX_RSFEC_PHY5_LINK_TIMEOUT_CFG (CSR_RX_RSFEC_BASE + 0x1210)
#define CSR_RX_RSFEC_PHY5_HEE_CFG (CSR_RX_RSFEC_BASE + 0x1214)
#define CSR_RX_RSFEC_PHY5_DIAG_CFG (CSR_RX_RSFEC_BASE + 0x1218)
#define CSR_RX_RSFEC_PHY5_DEGRADE_SER_CFG (CSR_RX_RSFEC_BASE + 0x121c)
#define CSR_RX_RSFEC_PHY5_DEGRADE_SER_SET (CSR_RX_RSFEC_BASE + 0x1220)
#define CSR_RX_RSFEC_PHY5_DEGRADE_SER_CLR (CSR_RX_RSFEC_BASE + 0x1224)
#define CSR_RX_RSFEC_PHY5_DEGRADE_SER_CW (CSR_RX_RSFEC_BASE + 0x1228)
#define CSR_RX_RSFEC_PHY5_PHY_BER_CFG (CSR_RX_RSFEC_BASE + 0x122c)
#define CSR_RX_RSFEC_PHY5_PHY_BER_SET (CSR_RX_RSFEC_BASE + 0x1230)
#define CSR_RX_RSFEC_PHY5_PHY_BER_CLR (CSR_RX_RSFEC_BASE + 0x1234)
#define CSR_RX_RSFEC_PHY5_PHY_BER_CW (CSR_RX_RSFEC_BASE + 0x1238)
#define CSR_RX_RSFEC_PHY5_HI_BER_SET (CSR_RX_RSFEC_BASE + 0x123c)
#define CSR_RX_RSFEC_PHY5_HI_BER_CLR (CSR_RX_RSFEC_BASE + 0x1240)
#define CSR_RX_RSFEC_PHY5_HI_BER_GAP (CSR_RX_RSFEC_BASE + 0x1244)
#define CSR_RX_RSFEC_PHY5_SD_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1250)
#define CSR_RX_RSFEC_PHY5_SD_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1254)
#define CSR_RX_RSFEC_PHY5_SF_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1258)
#define CSR_RX_RSFEC_PHY5_SF_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x125c)
#define CSR_RX_RSFEC_PHY5_SD_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1260)
#define CSR_RX_RSFEC_PHY5_SD_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1264)
#define CSR_RX_RSFEC_PHY5_SF_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1268)
#define CSR_RX_RSFEC_PHY5_SF_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0x126c)
#define CSR_RX_RSFEC_PHY5_SD_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1270)
#define CSR_RX_RSFEC_PHY5_SD_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1274)
#define CSR_RX_RSFEC_PHY5_SF_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1278)
#define CSR_RX_RSFEC_PHY5_SF_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x127c)
#define CSR_RX_RSFEC_PHY5_SD_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1280)
#define CSR_RX_RSFEC_PHY5_SD_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1284)
#define CSR_RX_RSFEC_PHY5_SF_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1288)
#define CSR_RX_RSFEC_PHY5_SF_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x128c)
#define CSR_RX_RSFEC_PHY5_STATUS (CSR_RX_RSFEC_BASE + 0x1290)
#define CSR_RX_RSFEC_PHY5_RX_HIS_STATUS (CSR_RX_RSFEC_BASE + 0x1294)
#define CSR_RX_RSFEC_PHY5_BOND_STATUS (CSR_RX_RSFEC_BASE + 0x1298)
#define CSR_RX_RSFEC_PHY5_ISO_STATUS (CSR_RX_RSFEC_BASE + 0x129c)
#define CSR_RX_RSFEC_PHY5_TIME_OUT_STATUS (CSR_RX_RSFEC_BASE + 0x12a0)
#define CSR_RX_RSFEC_PHY5_IDLE_CHK_ERR_CNT (CSR_RX_RSFEC_BASE + 0x12a4)
#define CSR_RX_RSFEC_PHY5_RX_INV_BLOCK_CNT (CSR_RX_RSFEC_BASE + 0x12a8)
#define CSR_RX_RSFEC_PHY5_ERR_BIT_CNT (CSR_RX_RSFEC_BASE + 0x12ac)
#define CSR_RX_RSFEC_PHY5_ERR_SYM_CNT (CSR_RX_RSFEC_BASE + 0x12b0)
#define CSR_RX_RSFEC_PHY5_DEC_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1300)
#define CSR_RX_RSFEC_PHY5_ERR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1304)
#define CSR_RX_RSFEC_PHY5_CORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1308)
#define CSR_RX_RSFEC_PHY5_UNCORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x130c)
#define CSR_RX_RSFEC_PHY5_CORR_LANE_SYM_CNT_ (CSR_RX_RSFEC_BASE + 0x1310)
#define CSR_RX_RSFEC_PHY5_LANE_COR0_CNT_ (CSR_RX_RSFEC_BASE + 0x1318)
#define CSR_RX_RSFEC_PHY5_LANE_COR1_CNT_ (CSR_RX_RSFEC_BASE + 0x1320)
#define CSR_RX_RSFEC_PHY6_CONTROL (CSR_RX_RSFEC_BASE + 0x1400)
#define CSR_RX_RSFEC_PHY6_HISER_CFG (CSR_RX_RSFEC_BASE + 0x1404)
#define CSR_RX_RSFEC_PHY6_HISER_GAP_CFG (CSR_RX_RSFEC_BASE + 0x1408)
#define CSR_RX_RSFEC_PHY6_ERR_STA_CFG (CSR_RX_RSFEC_BASE + 0x140c)
#define CSR_RX_RSFEC_PHY6_LINK_TIMEOUT_CFG (CSR_RX_RSFEC_BASE + 0x1410)
#define CSR_RX_RSFEC_PHY6_HEE_CFG (CSR_RX_RSFEC_BASE + 0x1414)
#define CSR_RX_RSFEC_PHY6_DIAG_CFG (CSR_RX_RSFEC_BASE + 0x1418)
#define CSR_RX_RSFEC_PHY6_DEGRADE_SER_CFG (CSR_RX_RSFEC_BASE + 0x141c)
#define CSR_RX_RSFEC_PHY6_DEGRADE_SER_SET (CSR_RX_RSFEC_BASE + 0x1420)
#define CSR_RX_RSFEC_PHY6_DEGRADE_SER_CLR (CSR_RX_RSFEC_BASE + 0x1424)
#define CSR_RX_RSFEC_PHY6_DEGRADE_SER_CW (CSR_RX_RSFEC_BASE + 0x1428)
#define CSR_RX_RSFEC_PHY6_PHY_BER_CFG (CSR_RX_RSFEC_BASE + 0x142c)
#define CSR_RX_RSFEC_PHY6_PHY_BER_SET (CSR_RX_RSFEC_BASE + 0x1430)
#define CSR_RX_RSFEC_PHY6_PHY_BER_CLR (CSR_RX_RSFEC_BASE + 0x1434)
#define CSR_RX_RSFEC_PHY6_PHY_BER_CW (CSR_RX_RSFEC_BASE + 0x1438)
#define CSR_RX_RSFEC_PHY6_HI_BER_SET (CSR_RX_RSFEC_BASE + 0x143c)
#define CSR_RX_RSFEC_PHY6_HI_BER_CLR (CSR_RX_RSFEC_BASE + 0x1440)
#define CSR_RX_RSFEC_PHY6_HI_BER_GAP (CSR_RX_RSFEC_BASE + 0x1444)
#define CSR_RX_RSFEC_PHY6_SD_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1450)
#define CSR_RX_RSFEC_PHY6_SD_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1454)
#define CSR_RX_RSFEC_PHY6_SF_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1458)
#define CSR_RX_RSFEC_PHY6_SF_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x145c)
#define CSR_RX_RSFEC_PHY6_SD_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1460)
#define CSR_RX_RSFEC_PHY6_SD_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1464)
#define CSR_RX_RSFEC_PHY6_SF_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1468)
#define CSR_RX_RSFEC_PHY6_SF_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0x146c)
#define CSR_RX_RSFEC_PHY6_SD_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1470)
#define CSR_RX_RSFEC_PHY6_SD_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1474)
#define CSR_RX_RSFEC_PHY6_SF_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1478)
#define CSR_RX_RSFEC_PHY6_SF_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x147c)
#define CSR_RX_RSFEC_PHY6_SD_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1480)
#define CSR_RX_RSFEC_PHY6_SD_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1484)
#define CSR_RX_RSFEC_PHY6_SF_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1488)
#define CSR_RX_RSFEC_PHY6_SF_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x148c)
#define CSR_RX_RSFEC_PHY6_STATUS (CSR_RX_RSFEC_BASE + 0x1490)
#define CSR_RX_RSFEC_PHY6_RX_HIS_STATUS (CSR_RX_RSFEC_BASE + 0x1494)
#define CSR_RX_RSFEC_PHY6_BOND_STATUS (CSR_RX_RSFEC_BASE + 0x1498)
#define CSR_RX_RSFEC_PHY6_ISO_STATUS (CSR_RX_RSFEC_BASE + 0x149c)
#define CSR_RX_RSFEC_PHY6_TIME_OUT_STATUS (CSR_RX_RSFEC_BASE + 0x14a0)
#define CSR_RX_RSFEC_PHY6_IDLE_CHK_ERR_CNT (CSR_RX_RSFEC_BASE + 0x14a4)
#define CSR_RX_RSFEC_PHY6_RX_INV_BLOCK_CNT (CSR_RX_RSFEC_BASE + 0x14a8)
#define CSR_RX_RSFEC_PHY6_ERR_BIT_CNT (CSR_RX_RSFEC_BASE + 0x14ac)
#define CSR_RX_RSFEC_PHY6_ERR_SYM_CNT (CSR_RX_RSFEC_BASE + 0x14b0)
#define CSR_RX_RSFEC_PHY6_DEC_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1500)
#define CSR_RX_RSFEC_PHY6_ERR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1508)
#define CSR_RX_RSFEC_PHY6_CORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1510)
#define CSR_RX_RSFEC_PHY6_UNCORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1518)
#define CSR_RX_RSFEC_PHY6_CORR_LANE_SYM_CNT_ (CSR_RX_RSFEC_BASE + 0x1520)
#define CSR_RX_RSFEC_PHY6_LANE_COR0_CNT_ (CSR_RX_RSFEC_BASE + 0x1530)
#define CSR_RX_RSFEC_PHY6_LANE_COR1_CNT_ (CSR_RX_RSFEC_BASE + 0x1540)
#define CSR_RX_RSFEC_PHY7_CONTROL (CSR_RX_RSFEC_BASE + 0x1600)
#define CSR_RX_RSFEC_PHY7_HISER_CFG (CSR_RX_RSFEC_BASE + 0x1604)
#define CSR_RX_RSFEC_PHY7_HISER_GAP_CFG (CSR_RX_RSFEC_BASE + 0x1608)
#define CSR_RX_RSFEC_PHY7_ERR_STA_CFG (CSR_RX_RSFEC_BASE + 0x160c)
#define CSR_RX_RSFEC_PHY7_LINK_TIMEOUT_CFG (CSR_RX_RSFEC_BASE + 0x1610)
#define CSR_RX_RSFEC_PHY7_HEE_CFG (CSR_RX_RSFEC_BASE + 0x1614)
#define CSR_RX_RSFEC_PHY7_DIAG_CFG (CSR_RX_RSFEC_BASE + 0x1618)
#define CSR_RX_RSFEC_PHY7_DEGRADE_SER_CFG (CSR_RX_RSFEC_BASE + 0x161c)
#define CSR_RX_RSFEC_PHY7_DEGRADE_SER_SET (CSR_RX_RSFEC_BASE + 0x1620)
#define CSR_RX_RSFEC_PHY7_DEGRADE_SER_CLR (CSR_RX_RSFEC_BASE + 0x1624)
#define CSR_RX_RSFEC_PHY7_DEGRADE_SER_CW (CSR_RX_RSFEC_BASE + 0x1628)
#define CSR_RX_RSFEC_PHY7_PHY_BER_CFG (CSR_RX_RSFEC_BASE + 0x162c)
#define CSR_RX_RSFEC_PHY7_PHY_BER_SET (CSR_RX_RSFEC_BASE + 0x1630)
#define CSR_RX_RSFEC_PHY7_PHY_BER_CLR (CSR_RX_RSFEC_BASE + 0x1634)
#define CSR_RX_RSFEC_PHY7_PHY_BER_CW (CSR_RX_RSFEC_BASE + 0x1638)
#define CSR_RX_RSFEC_PHY7_HI_BER_SET (CSR_RX_RSFEC_BASE + 0x163c)
#define CSR_RX_RSFEC_PHY7_HI_BER_CLR (CSR_RX_RSFEC_BASE + 0x1640)
#define CSR_RX_RSFEC_PHY7_HI_BER_GAP (CSR_RX_RSFEC_BASE + 0x1644)
#define CSR_RX_RSFEC_PHY7_SD_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1650)
#define CSR_RX_RSFEC_PHY7_SD_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1654)
#define CSR_RX_RSFEC_PHY7_SF_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1658)
#define CSR_RX_RSFEC_PHY7_SF_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x165c)
#define CSR_RX_RSFEC_PHY7_SD_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1660)
#define CSR_RX_RSFEC_PHY7_SD_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1664)
#define CSR_RX_RSFEC_PHY7_SF_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1668)
#define CSR_RX_RSFEC_PHY7_SF_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0x166c)
#define CSR_RX_RSFEC_PHY7_SD_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1670)
#define CSR_RX_RSFEC_PHY7_SD_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1674)
#define CSR_RX_RSFEC_PHY7_SF_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1678)
#define CSR_RX_RSFEC_PHY7_SF_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x167c)
#define CSR_RX_RSFEC_PHY7_SD_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1680)
#define CSR_RX_RSFEC_PHY7_SD_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1684)
#define CSR_RX_RSFEC_PHY7_SF_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1688)
#define CSR_RX_RSFEC_PHY7_SF_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x168c)
#define CSR_RX_RSFEC_PHY7_STATUS (CSR_RX_RSFEC_BASE + 0x1690)
#define CSR_RX_RSFEC_PHY7_RX_HIS_STATUS (CSR_RX_RSFEC_BASE + 0x1694)
#define CSR_RX_RSFEC_PHY7_BOND_STATUS (CSR_RX_RSFEC_BASE + 0x1698)
#define CSR_RX_RSFEC_PHY7_ISO_STATUS (CSR_RX_RSFEC_BASE + 0x169c)
#define CSR_RX_RSFEC_PHY7_TIME_OUT_STATUS (CSR_RX_RSFEC_BASE + 0x16a0)
#define CSR_RX_RSFEC_PHY7_IDLE_CHK_ERR_CNT (CSR_RX_RSFEC_BASE + 0x16a4)
#define CSR_RX_RSFEC_PHY7_RX_INV_BLOCK_CNT (CSR_RX_RSFEC_BASE + 0x16a8)
#define CSR_RX_RSFEC_PHY7_ERR_BIT_CNT (CSR_RX_RSFEC_BASE + 0x16ac)
#define CSR_RX_RSFEC_PHY7_ERR_SYM_CNT (CSR_RX_RSFEC_BASE + 0x16b0)
#define CSR_RX_RSFEC_PHY7_DEC_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1700)
#define CSR_RX_RSFEC_PHY7_ERR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1704)
#define CSR_RX_RSFEC_PHY7_CORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1708)
#define CSR_RX_RSFEC_PHY7_UNCORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x170c)
#define CSR_RX_RSFEC_PHY7_CORR_LANE_SYM_CNT_ (CSR_RX_RSFEC_BASE + 0x1710)
#define CSR_RX_RSFEC_PHY7_LANE_COR0_CNT_ (CSR_RX_RSFEC_BASE + 0x1718)
#define CSR_RX_RSFEC_PHY7_LANE_COR1_CNT_ (CSR_RX_RSFEC_BASE + 0x1720)

#endif